Temperature monitoring in a semiconductor device by thermocouples distributed in the contact structure

ABSTRACT

By forming thermocouples in a contact structure of a semiconductor device, respective extension lines of the thermocouples may be routed to any desired location within the die, without consuming valuable semiconductor area in the device layer. Thus, an appropriate network of measurement points of interest may be provided, while at the same time allowing the application of well-established process techniques and materials. Hence, temperature-dependent signals may be obtained from hot spots substantially without being affected by design constraints in the device layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to the formation of integratedcircuits, and, more particularly, to enhanced thermal sensing techniquesin semiconductor devices.

2. Description of the Related Art

The fabrication of integrated circuits requires a large number ofcircuit elements, such as transistors and the like, to be formed on agiven chip area according to a specified circuit layout. Generally, aplurality of process technologies are currently practiced, wherein, forcomplex circuitry, such as microprocessors, storage chips, ASICs(application specific ICs) and the like, CMOS technology is currentlyone of the most promising approaches due to the superior characteristicsin view of operating speed and/or power consumption and/or costefficiency. During the fabrication of complex integrated circuits usingCMOS technology, millions of complementary transistors, i.e., N-channeltransistors and P-channel transistors, are formed on a substrateincluding a crystalline semiconductor layer. A MOS transistor,irrespective of whether an N-channel transistor or a P-channeltransistor is considered, comprises so-called PN junctions that areformed by an interface of highly doped drain and source regions with aninversely or weakly doped channel region disposed between the drainregion and the source region.

The conductivity of the channel region, i.e., the drive currentcapability of the conductive channel, is controlled by a gate electrodeformed above the channel region and separated therefrom by a thininsulating layer. The conductivity of the channel region, upon formationof a conductive channel due to the application of an appropriate controlvoltage to the gate electrode, depends on the dopant concentration, themobility of the majority charge carriers and, for a given extension ofthe channel region in the transistor width direction, on the distancebetween the source and drain regions, which is also referred to aschannel length. Hence, in combination with the capability of rapidlycreating a conductive channel below the insulating layer uponapplication of the control voltage to the gate electrode, theconductivity of the channel region substantially determines theperformance of the MOS transistors.

The increased packing density of integrated circuits resulting from thereduced device dimensions has given rise to the incorporation of moreand more functions into a single semiconductor die. Furthermore, thereduced feature sizes may also be accompanied by reduced switchingspeeds of the individual transistors, thereby contributing to increasedpower consumption in MOS circuits, since the reduced switching speedsallow the operation of the transistors at higher switching frequencies,which in turn increases the power consumption of the entire device. Insophisticated applications using densely packed integrated circuits, theheat generation may reach extremely high values due to the dynamiclosses caused by the high operating frequency, in combination with asignificant static power consumption of highly scaled transistor devicesowing to increased leakage currents that may stem from extremely thingate dielectrics, short channel effects and the like. Therefore, greatefforts are being made in order to reduce overall power consumption byrestricting the usage of high performance transistors, which usuallycause higher heat generation, to performance-critical signal paths inthe circuit design, while using less critical devices in other circuitareas. Moreover, appropriate mechanisms may be implemented to operatecertain circuit portions “on demand” and control local or globaloperating conditions, depending on the thermal situation in thesemiconductor die. Since external heat management systems may not enablereliable estimation of the die-internal temperature distribution, due tothe delayed thermal response of the package of the semiconductor deviceand the possibly insufficient spatial temperature resolution, respectiveexternal concepts may have to be designed to take into considerationthese restrictions and provide sufficient operational margins withrespect to heat control, or risk overheating and thus possiblydestruction of specific critical circuit portions.

Manufacturers of semiconductor products, therefore, increasingly preferaccurate internal temperature measurements that do not substantiallydepend on external device conditions and dedicated thermal hardwarecomponents that may be subject to external tampering, while alsoavoiding the slow thermal response via the device package. For thispurpose, sophisticated heat monitoring regimes may typically beincorporated into the overall design of the integrated circuit, whichmay enable a device-internal heat management, irrespective of externalconditions. Thus, die-internal temperature measurements are typicallyperformed in complex devices, such as CPUs, ASICs and the like, so as toprovide device-internal data for controlling the overall operation byreducing operating frequency, switching off respective circuit portionsand the like. A respective die-internal heat management system,therefore, relies on accurate temperature measurement. In manyapproaches, techniques for measuring the die-internal temperature ortemperature gradients are accomplished by positioningtemperature-sensitive circuits around the die in order to locallydetermine the temperature. The various temperature measurements may thenbe combined to provide a global measure of the die temperature, whilealso allowing a local assessment of the thermal conditions across thedie, depending on the distribution of the temperature-sensitivecircuits. Hence, the higher a spatial resolution of the measuredtemperature profile is desired, the more temperature-sensing locationsand hence respective sensor circuits are required. The incorporation ofa plurality of temperature-sensitive circuits, however, may result in asignificant “consumption” of valuable real estate of the semiconductordie, which may typically cause a “competitive” situation during circuitdesign between actual circuit portions and temperature-sensitive areas.Therefore, frequently, the temperature-sensitive circuit portions aretreated with reduced priority compared to the “actual” circuit portions,which may finally result in a circuit design in which thetemperature-sensitive circuits are positioned in less than idealtemperature sensing locations. For instance, the design ofperformance-critical circuit portions of the device that may be operatedat higher speed or frequencies may not be compatible with the provisionsof sensor elements in these critical areas, for example, due toundesired lengthening of the signal routing and reduction of speed.Hence, although these performance-critical areas usually generate asignificantly higher amount of heat, the temperature of such “hot spots”may not be reliably measured, since the temperature-sensitive circuitsare positioned by the design constraints at distant locations.Therefore, in this case, damage of the performance-critical areas mayoccur or respective heat management strategies may be required to takeinto account the discrepancy of the measurement data and the actualthermal conditions in the performance-critical areas. Similarly, thethermal response of the temperature-sensitive circuits may be affectedby the shielding effect of materials and structures that may be providedin the vicinity of the temperature-sensitive circuits. For example, dueto the reduced heat dissipation capability of SOI (silicon-on-insulator)devices caused by the buried insulating layer, on which the actual“active” device layer is formed, the corresponding sensing of themomentary temperature in SOI devices is of particular importance,wherein, additionally, the design-dependent positioning of thetemperature-sensitive circuits may further contribute to a lessefficient overall temperature management in sophisticated SOI devices.

Frequently, for thermal sensing applications, an appropriate diodestructure may be used wherein the corresponding characteristic of thediode may permit information to be obtained on the thermal conditions inthe vicinity of the diode structure. The sensitivity and the accuracy ofthe respective measurement data obtained on the basis of the diodestructure may significantly depend on the diode characteristic, i.e., onthe diode's current/voltage characteristic, which may depend ontemperature and other parameters. For thermal sensing applications, itmay, therefore, typically be desirable to provide a substantially“ideal” diode characteristic in order to provide the potential forprecisely estimating the temperature conditions within the semiconductordevice. In SOI devices, a corresponding diode structure, i.e., therespective PN junction, is typically formed in the substrate materiallocated below the buried insulating layer, above which is formed the“active” semiconductor layer used for forming therein the transistorelements. Thus, in addition to the shielding effect of the buriedinsulating layer, at least some additional process steps may berequired, for instance, for etching through the semiconductor layer or acorresponding trench isolation area and through the buried insulatinglayer in order to expose the crystalline substrate material, therebycontributing to the overall process complexity. Furthermore, thetemperature-sensing diodes, in combination with an appropriateevaluation circuit, may also be subject to similar design constraints asdescribed above, irrespective of whether a bulk architecture or an SOIarchitecture is considered. Hence, currently employed die-internaltemperature monitoring mechanisms, although providing significantadvantages over external temperature management systems, may suffer fromincreased die area consumption, reduced proximity to hot spots andthermal isolation of the temperature-sensitive circuits, as will bebriefly discussed with reference to FIG. 1.

FIG. 1 schematically illustrates a top view of a semiconductor device100, which may be provided in the form of a semiconductor die includingone or more complex circuits, such as CPU's, memory devices,input/output circuitry and the like. As previously explained, thesemiconductor device 100 may have, depending on the overall designcriteria, circuit portions of different performance characteristics,such as speed-critical signal paths and the like. Moreover, highly densecircuit areas may be provided, for instance, in the form of memoryareas, such as static RAM areas, dynamic RAM areas and the like. Forexample, a device region 110 may represent an area including a pluralityof high performance circuit elements, such as transistor elements havinga reduced channel length in combination with a thin gate insulationlayer, which may contribute to increased leakage currents, as previouslyexplained. Consequently, upon operation of the device 100, significantheat may be generated in the region 110. Furthermore, an area 111 mayrepresent a device area, in which the overall circuit design may imposetight restrictions with respect to the incorporation of temperaturemonitoring circuitry and sensors, thereby requiring a certain distancewith respect to the high performance region 110. Furthermore, at certaindevice areas, which are compatible with the overall circuit design, aplurality of temperature-sensitive circuits 120 are typically provided,which include temperature-sensitive elements, such as diodes and thelike, in combination with respective support circuitry to receive andevaluate or process temperature-dependent signals. It should beappreciated that the overall structure of the semiconductor device 100may comprise any appropriate substrate material, such as silicon, andthe like, above which is typically formed an appropriate semiconductorlayer, such as a silicon-based material in and above which respectivecircuit elements, such as transistors, capacitors, diodes and the like,are formed in accordance with the technology standard underconsideration.

The electrical connection of the individual circuit elements usually maynot be accomplished on the same level in which the circuit elements aremanufactured, but may require a plurality of additional wiring layers,also referred to as metallization layers, in which highly conductivemetal lines which may comprise appropriate metals, such as aluminum,copper and the like, may be routed according to the specified circuitlayout. The plurality of metallization layers are interconnected witheach other by respective vias, that is, vertical metal-filled contactelements connecting metal lines and metal regions of adjacent stackedmetallization layers. Furthermore, a so-called contact structure isprovided on the basis of an appropriate dielectric material whichencloses the circuit elements, such as the transistors and capacitorsand the like, and which acts as an interface to the very firstmetallization layer. Within the contact structure, respective contactelements or contact plugs are positioned, which connect to respectivecontact areas of the circuit elements, such as gate electrodes, drainand source regions of transistors and the like. For example, frequently,a combination of silicon nitride, which might act as an etch stopmaterial, followed by silicon dioxide, are common interlayer dielectricmaterials for the contact structure.

Thus, as previously explained, during operation of the semiconductordevice 100, heat is generated in a spatially varying manner, dependingon the position of performance-driven circuit portions, such as thedevice region 110 and the overall configuration of the semiconductordevice 100. For instance, in moderately complex systems, in addition tohighly complex digital circuits including extremely fast switchingtransistor elements, in other cases, circuit portions of different powerlevels may be integrated into the same semiconductor die, thereby alsocreating a different amount of heat during operation. Since the overallcircuit design may not allow positioning of the temperature-sensitivecircuits 120 at desired device areas, such as in the vicinity of theperformance-driven circuit region 110, without requiring significantdesign modification, which may be accompanied by performance loss andthe like, a reliable detection of the actual temperature in criticaldevice areas may be difficult. Furthermore, coverage of the entire diearea, except for less sensitive areas, such as the area 111, may requirea plurality of temperature-sensitive circuits 120, which mayconventionally consume valuable area in the device layer, i.e., in thesemiconductor layer, which also accommodates the actual circuitelements. Hence, in conventional devices, the spatial resolution, aswell as the accuracy of temperature-related information, may be lowerthan is desirable.

The present disclosure is directed to various methods and devices thatmay avoid, or at least reduce, the effects of one or more of theproblems identified above.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an exhaustive overview of the invention. It is notintended to identify key or critical elements of the invention or todelineate the scope of the invention. Its sole purpose is to presentsome concepts in a simplified form as a prelude to the more detaileddescription that is discussed later.

Generally, the subject matter disclosed herein provides semiconductordevices and methods for enhanced temperature sensing capabilities withina semiconductor die, while reducing area consumption and/or providinghigher efficiency of evaluating temperatures of critical device regionsand/or reducing thermal isolation, which may be caused by the presenceof inappropriate materials between the point of interest and the actualsensor location. For this purpose, the present disclosure contemplatestemperature-sensitive elements such as thermocouples which may bepositioned in the contact structure, i.e., in the dielectric materialprovided between the device layer and the metallization system, therebyreducing the overall amount of required semiconductor area, since theactual temperature-sensitive components may be positioned above thesemiconductor material. Furthermore, the contact structure is in closeproximity to the actual circuit elements, thereby providing asubstantially non-delayed thermal response of the temperature-sensitiveelements and also maintaining thermal isolation of respectivemeasurement points of interest at a low level. Moreover, thetemperature-sensitive elements may be appropriately routed within thecontact structure, for instance in the form of respective extensionlines of thermocouples, thereby providing the potential for obtaining atemperature-sensitive signal from specified points of interest, while arespective associated circuitry for receiving the temperature-dependentsignal may be positioned at any appropriate remote location. Thus, byappropriately routing the temperature-sensitive elements in the contactstructure, a high degree of coverage of areas of interest may beaccomplished, since the design constraints imposed by the contactstructure are significantly more relaxed compared to the actual devicelayer, so that measurement points may be appropriately positioned abovedevice areas, the design constraints of which may not allow theprovision of temperature-sensitive circuitry in the device layer aspreviously explained. For example, thermocouple loops may be routedacross the semiconductor die within the contact structure, while aninterface to the associated support circuitry for thetemperature-sensitive elements may be positioned at any appropriatelocation that is compatible with the overall circuit design.

One illustrative semiconductor device disclosed herein comprises asemiconductor layer formed above a substrate and a circuit elementformed in the semiconductor layer, wherein the circuit element comprisesa contact region. Moreover, the semiconductor device comprises aninterlayer dielectric material formed above the circuit element and acontact element formed in the interlayer dielectric material so as toconnect to the contact region. Finally, the semiconductor devicecomprises a temperature-sensitive element formed in the interlayerdielectric material, wherein the temperature-sensitive element isconfigured to provide a temperature-dependent signal.

A still further illustrative semiconductor device disclosed hereincomprises a plurality of circuit elements formed in and above asemiconductor layer and an interlayer dielectric material enclosing theplurality of circuit elements. Furthermore, the semiconductor devicecomprises a thermocouple formed in the interlayer dielectric material.

One illustrative method disclosed herein comprises selecting a firstlocation in an overall circuit design of a semiconductor device, whereinthe first location corresponds to a device area for receiving atemperature signal by a temperature evaluation circuit of thesemiconductor device. The method further comprises selecting a secondlocation as a measurement site of interest in the semiconductor deviceand forming a temperature-sensitive element in an interlayer dielectricmaterial that is formed between circuit elements of the semiconductordevice and a first metallization layer of the semiconductor device,wherein the temperature-sensitive element comprises conductive linesextending from the first location to the second location.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIG. 1 schematically illustrates a top view of a conventionalsemiconductor die including a plurality of temperature sensitivecircuits formed in the device layer and positioned in accordance withdesign constraints in the device layer;

FIG. 2 a schematically illustrates a top view of a semiconductor diecomprising a thermocouple formed in a contact structure positioned abovethe device layer, thereby enabling the routing of the thermocoupleextension lines to a point of interest in the contact structure,according to illustrative embodiments;

FIG. 2 b schematically illustrates a semiconductor die comprising aplurality of locations for accommodating respective support circuitryfor evaluating temperature-dependent signals obtained from a pluralityof thermocouples extending within the contact structure so as to obtaina high degree of coverage, according to further illustrativeembodiments;

FIG. 2 c schematically illustrates a top view of a thermocoupleconnected to the device layer, according to illustrative embodiments;

FIGS. 2 d-2 f schematically illustrate cross-sectional views of aportion of a thermocouple and respective contact plugs connectingextension lines to the device layer, according to illustrativeembodiments;

FIGS. 2 g-2 i schematically illustrate top views of a portion of athermocouple in accordance with illustrative embodiments disclosedherein;

FIGS. 2 j-2 n schematically illustrate cross-sectional views of a “tip”portion of a thermocouple during various manufacturing stages in forminga respective interface between two different conductive materials,according to illustrative embodiments;

FIG. 2 o schematically illustrates a cross-sectional view of a “tip”portion and a contact area of a thermocouple formed by an electrolessplating technique, according to further illustrative embodiments;

FIGS. 2 p-2 r schematically illustrate cross-sectional views of a “tip”portion of a thermocouple, wherein respective metal lines of thethermocouple are formed by subsequent patterning steps, according toillustrative embodiments;

FIG. 3 schematically illustrates a top view of a semiconductor dieincluding a plurality of thermocouples and at least one well-definedreference point, according to still further illustrative embodiments;and

FIG. 4 schematically illustrates a top view of a portion of asemiconductor device including a plurality of thermocouples, which maybe subject to substantially the same temperature conditions and whichmay be appropriately electrically connected so as to enhance outputpower, output voltage and the like, thereby improving temperaturecontrol of the respective semiconductor area, according to still furtherillustrative embodiments.

While the subject matter disclosed herein is susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and are herein described indetail. It should be understood, however, that the description herein ofspecific embodiments is not intended to limit the invention to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

Various illustrative embodiments of the invention are described below.In the interest of clarity, not all features of an actual implementationare described in this specification. It will of course be appreciatedthat in the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

The present subject matter will now be described with reference to theattached figures. Various structures, systems and devices areschematically depicted in the drawings for purposes of explanation onlyand so as to not obscure the present disclosure with details that arewell known to those skilled in the art. Nevertheless, the attacheddrawings are included to describe and explain illustrative examples ofthe present disclosure. The words and phrases used herein should beunderstood and interpreted to have a meaning consistent with theunderstanding of those words and phrases by those skilled in therelevant art. No special definition of a term or phrase, i.e., adefinition that is different from the ordinary and customary meaning asunderstood by those skilled in the art, is intended to be implied byconsistent usage of the term or phrase herein. To the extent that a termor phrase is intended to have a special meaning, i.e., a meaning otherthan that understood by skilled artisans, such a special definition willbe expressly set forth in the specification in a definitional mannerthat directly and unequivocally provides the special definition for theterm or phrase.

Generally, the subject matter disclosed herein relates to enhancedtechniques for monitoring and/or controlling the temperaturedistribution in a semiconductor die by providing temperature-sensitiveelements within the contact structure of the semiconductor device so asto allow the positioning of the temperature-sensitive elements withreduced constraints compared to conventional approaches, in which thetemperature-sensitive circuits may typically be formed in the devicelayer, which may result in the above-explained deficiencies. Thus, by“using” the contact structure as a medium for forming thereintemperature-sensitive elements, close proximity to the points actuallygenerating heat may be accomplished, since the interlayer dielectricmaterial encloses the respective circuit elements, while also lessrestrictive design constraints may provide the potential ofappropriately routing the temperature-sensitive elements to any desiredmeasurement point. That is, the contact structure is typically“populated” by vertical contact plugs or elements and respectiveinterconnect structures, which may consume significantly less areacompared to the underlying circuit elements, thereby enabling anefficient routine of temperature-sensitive elements even at deviceareas, in which the underlying device layer exhibits a moderately highpacking density.

In some illustrative aspects disclosed herein, the temperature-sensitiveelements may be provided in the form of thermocouples, which may includeappropriate conductive lines within the interconnect structure, therebyenabling the application of well-established manufacturing techniquesand materials so as to obtain a high degree of compatibility withexisting semiconductor manufacturing regimes. Thermocouples are devicesin which the thermoelectric effect is used, wherein a temperaturegradient may result in a voltage in a conductor extending along a regionexhibiting a temperature gradient. In order to actually access thevoltage between two points of the conductive material at differenttemperatures, a further material is required for connecting to theconductor under consideration, wherein the additional conductor is alsosubject to the influence of the temperature gradient, which may cancelthe net voltage, if the same material would be used for both conductors.Hence, different conductive materials have to be used, which exhibit adifferent degree of thermoelectric effect, thereby obtaining a netvoltage that is indicative of the respective temperature gradient.Consequently, by appropriately routing a respective “couple” ofconductors from a location, at which the voltage may be detected andwhich may have a specific temperature to a point of interest, forinstance, a high temperature spot in the semiconductor device, thetemperature thereof may be evaluated on the basis of the temperaturegradient, while an appropriate routing regime for respective conductivelines of the thermocouple may provide the possibility of thermallymonitoring any desired point in the semiconductor die, without consumingareas in the device layer, i.e., in the semiconductor layer, in whichare formed the actual circuit elements. Moreover, a variety ofthermocouples are available, that is, respective conductive materials inthe form of metal-containing materials and the like, which may cover abroad range of temperatures, wherein a plurality of conductive materialsmay be available that may also be used in semiconductor manufacturingtechniques, thereby providing a high degree of compatibility withexisting technologies. For example, copper, constantan, i.e., a coppernickel alloy, platinum, rhodium and the like, may represent appropriatematerials for forming thermocouples which are also partially involved inmanufacturing techniques of modern semiconductor devices or which may atleast be compatible with respective processes. Hence, appropriatematerials and patterning and routing regimes may be used in the contactlevel of a semiconductor device, while a respective support circuitry,which may be provided in the form of appropriate analog and digitalcircuit portions, may be positioned at any appropriate location withinthe die, wherein temperature-related aspects may also be taken intoconsideration when selecting an appropriate position for the supportcircuitry. That is, the circuitry may be positioned in a die region thatprovides the desired temperature condition so as to obtain meaningfulmeasurement data with respect to a temperature gradient between thespecified position of the support circuitry and a measurement point ofinterest, such as a hot spot area and the like. In other cases, one ormore thermocouples may be efficiently routed to respective referencepositions, for instance, to define a cool junction area of well-definedtemperature conditions during operation of the device, which may enhancethe overall accuracy of the temperature monitoring.

Consequently, a dense network of thermal measurement sites may beefficiently integrated into a complex semiconductor product, while atthe same time reducing consumption of semiconductor area compared toconventional strategies and also enhancing overall accuracy.Simultaneously, appropriate materials and process techniques may be usedwith a high degree of compatibility with existing semiconductorprocesses so that, in some illustrative aspects, well-establishedtechniques may be used for patterning the contact structure withoutrequiring the implementation of additional processes.

It should be appreciated that the principles disclosed herein areadvantageous for complex integrated semiconductor devices such as CPUsand the like. Here, due to the complex circuit design, a high packingdensity, in combination with performance-driven circuit regions, mayhave to be provided so that enhanced coverage and accuracy oftemperature monitoring and controlling may significantly contribute tooverall enhanced device performance. The principles disclosed hereinmay, however, also be advantageously applied to any complexsemiconductor devices, such as complex systems on a single chip, whichmay include analog circuitry in combination with digital circuitryand/or low voltage circuits in combination with high voltage circuitsand the like, since, also in these cases, the respective contactstructure may be advantageously used for positioning therein appropriatetemperature-sensitive elements with increased accuracy and coverage.Thus, unless specifically set forth in the description or the appendedclaims, the principles disclosed herein should not be considered asbeing restricted to a specific design of a semiconductor device.

FIG. 2 a schematically illustrates a top view of a semiconductor device200, which may represent any semiconductor device including circuitportions formed on the basis of circuit elements (not shown), which maybe formed in and above an appropriate semiconductor layer, such as asilicon-based layer, as the vast majority of complex integrated circuitsare currently, and will be in the near future, formed on the basis ofsilicon material. It should be appreciated that the respectivesemiconductor layer may, however, be comprised of any other appropriatematerial or material composition, depending on the overall devicerequirements. In the embodiment shown, the semiconductor device 200 mayrepresent a semiconductor die which may comprise a substrate, asemiconductor layer and respective circuit elements which will bedescribed later on in more detail, wherein the circuit elements may begrouped into respective functional blocks in accordance with the designof the semiconductor device under consideration. For instance, in therespective semiconductor layer, a region 211 may represent a functionalarea in which the presence of other functional elements, such astemperature-sensing elements, may not be compatible with designconstraints, as previously explained. Nevertheless, within or in thevicinity of the area 211, a measurement site of interest 210 may beprovided, which, for instance, may represent a region of increasedtemperature generation during operation of the semiconductor device 200.For example, the measurement site 210, which may also be referred to asa measurement location, may represent an area including a speed-criticalsignal path or high voltage circuit elements, which may result inenhanced heat generation during operation. It should be appreciated thata “location” in the semiconductor device 200 may be understood herein asa specified position and a corresponding “neighborhood,” which may rangefrom several micrometers to several tenths or hundreds of micrometers,depending on the lateral extension of the respective circuit elementsdefining a temperature-sensitive element. As previously explained, therespective circuit elements defining the areas 211 and the measurementsite 210 may be enclosed by an appropriate dielectric material which maybe referred to as an interlayer dielectric material, which separates thecircuit elements from actual metallization levels, in whichlayer-internal metal lines may be routed in accordance with the overallcircuit layout. Thus, the respective interlayer dielectric material maycomprise a plurality of “vertical” contact elements or plugs whichconnect at one end to circuit elements and connect at the other end torespective metal regions in the very first metallization layer.

It should be appreciated that a plurality of interconnect structures mayalso be provided within the interlayer dielectric material so as toconnect different circuit elements or different contact regions of thesame circuit element without providing a connection to the overlyingfirst metallization layer. However, compared to the area consumed bycircuit elements in the device layer, the area occupied by respectivecontact plugs and interconnect structures in the interlayer dielectricmaterial is significantly less, thereby providing available space forone or more temperature-sensitive elements 221, which in someillustrative embodiments, may be provided in the form of thermocouples,i.e., conductive lines of appropriate material composition so as toallow the detection of a temperature-dependent voltage. The one or moretemperature sensitive elements 221 may be connected to one or moreappropriate support circuits 220, which may be positioned at anyappropriate location in the device level so as to be compatible withdesign and temperature considerations. The temperature sensitiveelements 221 may comprise an extension portion 221E which extends fromabove the circuit 220 to the measurement site of interest 210 and whichconnects to an interface portion 221I in which an interface is formedbetween a first conductive line 221A and a second conductive line 221B,which are comprised of different conductive materials. For example, fora thermocouple of type T, the element 221 may comprise the metal line221A in the form of a copper material, while the metal line 221B may beprovided in the form of a constantan, that is, a copper nickel alloy. Inthis case, the element 221A may be appropriate for being operated with atemperature range from approximately −200° C. to approximately +300° C.,wherein a voltage of approximately 43 micro volts per ° C. oftemperature difference between the interface portion 221I and thetermination of the extension portion 221E may be obtained. That is, fora temperature difference between the measurement location 210 and theregion corresponding to the support circuitry 220 of 100° C., a voltageof approximately of 4.3 millivolt (mV) may be obtained. It should beappreciated that a plurality of conductive materials, such as silver,tungsten, nickel alloys, cobalt, molybdenum, gold, platinum, rhodium andthe like, may be used, wherein many of these materials may already beused during the manufacturing of complex semiconductor devices. In othercases, appropriate semiconductor materials may also be used incombination with a metal or in combination with other semiconductormaterials so as to provide an appropriate thermocouple positioned withinthe contact structure of the device 200.

The semiconductor device 200 may be formed on the basis ofwell-established process techniques, when the device level isconsidered, wherein, however, contrary to conventional strategies, thesupport circuit 220 may be appropriately adapted to the requirements ofthe temperature-sensitive elements 221. That is, appropriate analogand/or digital circuit portions may be provided to receive thetemperature-dependent signal from the elements 221 and perform anappropriate evaluation of the temperature-dependent signal, which may beaccomplished on the basis of an appropriate control unit (not shown)which may control the operation of the device 200 on the basis of theevaluated temperature signal. It should be appreciated that respectivecircuitry in combination with thermocouples is well established indiscrete circuit topologies and respective circuit topologies mayreadily be implemented into the overall design of the device 200.Furthermore, it is to be noted that the evaluation of thetemperature-dependent signals may be performed by an appropriatefunctional block of the device 200, which may not necessarily beimplemented within the support circuitry 220 but may also be implementedin a respective digital functional block, such as a CPU core, dedicatedtemperature control units and the like. It should be appreciated thatevaluation of a temperature-dependent signal may be understood such thatany type of signal processing may be performed in order to obtain atemperature-related signal, which may be used for the further monitoringor control of the device 200. For instance, evaluation of atemperature-dependent signal obtained by the element 221 may beaccomplished by comparing the signal, possibly after appropriate signalprocessing, with one or more threshold levels, each of which mayindicate a specific temperature-dependent status of the device 200.

Thus, after forming the respective circuit elements, an interlayerdielectric material may be formed, for instance, on the basis ofwell-established techniques and materials, wherein appropriatemanufacturing processes are incorporated to form the element 221, aswill be described later on in more detail. In some illustrativeembodiments, appropriate trenches may be formed, at least in a portionof the interlayer dielectric material which may be subsequently filledwith an appropriate conductive material, such as a metal-containingmaterial, to thereby form the metal lines 221A, 221B, wherein therouting of the trenches may be accomplished such that respective contactplugs (not shown) of actual circuit elements may be circumvented whilenevertheless positioning the interface portion 221I within the location210. For this purpose, appropriately designed lithography masks may beused when forming the respective trenches in an appropriate patterningsequence, as will be explained later on. After filling in theappropriate conductive materials to complete the temperature-sensitiveelements 221, further processing may be continued by forming arespective metallization structure on the basis of well-establishedtechniques, substantially without requiring significant modificationscompared to conventional strategies, except for appropriately connectingthe one or more support circuits 220 in accordance with the requiredoverall circuit layout. Hence, upon operation of the device 200,respective temperature-dependent information may be obtained frommeasurement sites of interest, such as the areas 210, substantiallywithout being restricted to any design constraints within the devicelevel, except for taking into consideration respective contact plugsprovided so as to connect to the circuit elements, above which theelement 221 is routed.

FIG. 2 b schematically illustrates the semiconductor device 200according to further illustrative embodiments, in which increasedcoverage of the overall die area may be obtained by providing aplurality of support circuits 220, wherein each of which may representan interface to a plurality of temperature sensitive elements 221 havinga configuration as is described with reference to FIG. 2 a. Thus, even ahigh degree of coverage may be accomplished in a sensitive device area,such as the area 211, in which design constraints may not allow theprovision of conventional temperature sensitive circuits. As shown,according to the principles disclosed herein, the reduced area consumedby actual interconnect structures and contact plugs in the interlayerdielectric material may provide a high degree of flexibility of routingthe respective extension portions 221E, while also allowing anappropriate positioning of the support circuit 220, which may also actas an area of “constant” temperature for a plurality of end points ofelements 221, the other end of which is positioned in the correspondingmeasurement sites of interest, such as the area 210, and the like. Thus,a respective network of measurement sites may be established within thesemiconductor device 200, the density of which may be selected inaccordance with device requirements, substantially without increasingthe overall lateral size of the device 200.

FIG. 2 c schematically illustrates a top view of a single element 221comprising the conductive lines 221A, 221B formed of differentconductive materials, thereby forming the interface portion 221I aspreviously explained. Furthermore, respective elements or plugs 222A and222B may be provided so as to connect to the respective conductive lines221A, 221B and also to contact areas of circuit elements in the supportcircuitry 220. In some illustrative embodiments, the contact elements222A, 222B may be comprised of the same material as the lines 221A, 221Bto which the elements 222A, 222B may be connected. For example, in someillustrative embodiments, the line 221A may be comprised of anyappropriate material, such as copper and, thus, the contact plug 222Amay also be comprised of copper. Similarly, the line 221B may becomprised of, for instance, constantan and, thus, the plug 222B may alsobe comprised of constantan. In this manner, any deleterious effects ofinterfaces formed by the lines 221A, 221B with any appropriate electrodematerial may be avoided, unless the temperature-dependent voltage iscoupled into a respective circuit element of the circuitry 220. In otherillustrative embodiments, the contact elements 222A, 222B may be formedof any other appropriate material, for instance, both elements 222A,222B may be formed of the same material, which may be the same ordifferent compared to one or both of the materials in the lines 221A,221B.

FIG. 2 d schematically illustrates a cross-sectional view of the device200 along the line IId, as indicated in FIG. 2 c. In the manufacturingstage shown in FIG. 2 d, the conductive lines 221A, 221B may not yet beprovided. Thus, in this manufacturing stage, the device 200 may comprisea substrate 201, which may be provided in the form of any appropriatematerial, as previously explained, above which may be formed asemiconductor layer 202. In and above the semiconductor layer 202 may beformed circuit elements, for instance, in the form of transistors,capacitors, resistors and the like, which are collectively indicated ascircuit elements 223. In the embodiment shown, the circuit elements 223may belong to the support circuitry 220, wherein, for convenience, anyother circuit elements, for instance, corresponding to the device areas211, 210, are not shown in FIG. 2 d. The circuit elements 223 maycomprise appropriate contact regions 223C to receive atemperature-dependent voltage or signal provided by the elements 221.For example, the contact region 223C may be comprised of a highly dopedsemiconductor material, metal-containing material, such as a metalsilicide, and the like. Furthermore, in this manufacturing stage, afirst portion of an interlayer dielectric material, for instance, in theform of an etch stop layer 203, may be formed above the semiconductorlayer 202 and the circuit elements 223. For instance, frequently, aninterlayer dielectric material comprised of silicon nitride, which mayact as an etch stop material and/or as a strain-inducing material insophisticated silicon-based semiconductor devices, in combination with asilicon dioxide material, may be used. It should be appreciated that thelayer 203 may represent any appropriate material or materials acting asa portion of an interlayer dielectric layer, depending on the specificrequirements for the device 200. In some illustrative embodiments, asshown, the layer 203 may be provided as a substantially conformal layer,thereby substantially resembling the surface topography created by thecircuit elements 223. In other cases, the layer 203 or a combination ofdifferent layers may be formed so as to obtain a substantially planarsurface topography in order to enhance the overall patterning of thelayer 203, as will be described later on in more detail. In themanufacturing stage shown, an etch mask, for instance, in the form of aresist mask 204 may be provided to define an opening corresponding tothe contact element 222B (FIG. 2 c).

The semiconductor device 200 as shown in FIG. 2 d may be formed on thebasis of substantially the same process technique as described withreference to FIG. 2 a. That is, after forming the circuit elements 223,for instance, in compliance with functional and layout requirements asdemanded by the support circuitry 220, and also by design requirementsas demanded by circuit elements in other device regions not involved inthe temperature control of the device 200, the layer 203 may be formed,for instance, on the basis of well-established chemical vapor deposition(CVD) techniques, for instance, plasma enhanced chemical vapordeposition (PECVD), which may typically be used in combination withsilicon nitride materials, silicon carbide materials and the like. Itshould be appreciated that, in sophisticated applications, the layer 203may be provided as a highly stressed material, at least in dedicatedcircuit areas, depending on the overall requirements. Next, the mask 204may be formed on the basis of well-established photolithographytechniques and an appropriate etch process may be performed to removematerial of the layer 203 and expose the underlying contact region 223C.For this purpose, a plurality of well-established etch recipes, such asplasma-assisted recipes and the like, are available in the art and maybe used. In some illustrative embodiments, respective openings in thelayer 203 may be patterned for the contact elements 222B, 222A in acommon process, while, in other cases, separate patterning processes maybe used, wherein, after each patterning process, a respective depositionstep may be performed to provide the desired material for the respectivecontact elements 222B, 222A, which may then be formed of differentmaterials.

Thus, after patterning the layer 203, an appropriate material may befilled in by an appropriate deposition technique. For instance, acopper-based material may be formed on the basis of well-establishedelectrochemical deposition techniques, wherein an appropriate seed layermay be formed by sputter deposition and the like. For example, based onthe etch mask 204, an appropriate seed layer may be deposited, which maythen be removed commonly with the etch mask 204 so that the seed layeris only provided within an opening in the dielectric layer 203. In someillustrative embodiments, the respective deposition process may beperformed as a highly directional deposition process, thereby providinga substantial amount of seed material at the bottom, i.e., on theexposed contact region 223C, while maintaining the amount of seedmaterial at horizontal portions of the mask 204 and a respective openingin the layer 203 at a low level. During a subsequent electroless platingprocess, the desired material, such as copper, may be filled from bottomto top in a highly localized manner. Thereafter, any residuals may beremoved by an appropriate selective etch process and subsequently thelayer 203 may be patterned again so as to form an opening correspondingto the contact element 222A. In other cases, when the contact openingsare formed in a common patterning process, the same seed material may beused for both openings. During the actual wet chemical deposition, oneof the openings may be masked and, thereafter, the other already filledopening may be masked during filling of the previously masked contactopening. It should be appreciated, however, that any other appropriatemanufacturing regime may be used for forming the contact elements 222A,222B. For instance, the same material may be used for the contact plugs222A, 222B, wherein any appropriate material may be used, such astungsten and the like. In other cases, the contact elements 222A, 222Bmay be formed in a common manufacturing process together with theconductive lines 221A, 221B, as will be described later on. It shouldfurther be appreciated that, depending on the material used, a barrierlayer may be formed prior to actually depositing a seed layer and theactual conductive material. For instance, if a direct contact ofcopper-based materials with the contact region 223C is consideredinappropriate, respective barrier materials, such as tantalum, tantalumnitride, titanium, titanium nitride and the like, may be provided.

FIG. 2 e schematically illustrates the semiconductor device 200 afterthe above-described process sequence. Hence, the contact plug 222B maybe formed in the dielectric layer 203, possibly in combination with anappropriate barrier material, if required. Therefore, the contact plug222B may provide a contact between the circuit elements 223 and one ofthe conductive lines, i.e., the conductive line 221B of the element 221still to be performed.

FIG. 2 f schematically illustrates the semiconductor device 200 in afurther advanced manufacturing stage. As shown, a further dielectriclayer 204 may be provided above the layer 203, wherein the layer 204 maycomprise one or more different materials, depending on the overalldevice requirements. The dielectric layers 203, 204 may form aninterlayer dielectric material, commonly referred to as material 205, ina portion of which, i.e., the dielectric layer 204, thetemperature-sensitive element 221 may be formed. In the embodimentshown, the conductive line 221B may be formed in the layer 204 so as toconnect to the contact plug 222B, wherein, as previously explained, insome illustrative embodiments, the plug 222B and the line 221B may becomprised of substantially the same material. In other cases, the actualinterface between the support circuitry 220 and the temperaturesensitive-element 221 may be defined by an interface between the plug222B and the line 221B, if comprised of different materials.Furthermore, if a direct contact of the layer 205 with the conductivematerial in the line 221B is considered inappropriate, an appropriatedielectric barrier material may be provided. Hence, if the increaseddiffusivity of copper atoms in silicon dioxide is consideredinappropriate, at least the sidewall portions of the conductive line221B may be covered by an appropriate material, such as silicon nitride,silicon carbide and the like, as will also be described in more detailin reference to FIGS. 2 j-2 o.

The semiconductor device 200 as shown in FIG. 2 f may be formed on thebasis of the following processes. After forming the contact plugs 222A,222B, the dielectric layer 204 may be deposited, for instance, on thebasis of well-established chemical vapor deposition (CVD) techniques,such as plasma enhanced CVD, thermally activated CVD and the like,wherein any appropriate material may be used, for instance, silicondioxide material that may be deposited on the basis of TEOS. Dependingon the overall surface topography, the layer 204 may be planarized, forinstance, by chemical mechanical polishing (CMP) and the like.Thereafter, an appropriate resist mask may be formed by well-establishedlithography techniques and subsequently an etch recipe may be used foretching through the layer 204, thereby using the layer 203 as anefficient etch stop material. Thereafter, the respective trench may befilled with a desired material, as specified above, wherein appropriatedeposition techniques may be used, such as CVD, electrochemicaldeposition techniques and the like. Thereafter, any excess material maybe removed, for instance, on the basis of CMP, etch techniques and thelike.

FIG. 2 g schematically illustrates a top view of the semiconductordevice 200 after the above-described process sequence. It should beappreciated that the interface portion 221I and a part of the lines221A, 221B is illustrated only. As shown, the conductive line 221B maybe formed so as to extend to a desired measurement site, as previouslyexplained, while the respective line 221A is still to be formed, asindicated by the dashed lines. Thus, a patterning sequence may beperformed to provide a corresponding trench, which then may be filledwith an appropriate material on the basis of deposition techniquessimilar to those used for the formation of the conductive line 221B.Thereafter, any excess material may be removed, for instance, by CMP andthe like so as to obtain electrically insulated lines 221A, 221B, exceptfor a common interface in the portion 221I.

FIG. 2 h schematically illustrates a top view of the device 200 afterthe end of the above-described process sequence. Hence, the conductivelines 221A, 221B, comprised of different conductive materials, may beformed in the interlayer dielectric material 205 and may be connected tothe support circuitry 220 by means of the contact plugs 222A, 222B,which may be comprised of the same or different materials as therespective lines 221A, 221B, as previously explained. It should beappreciated that the conductive lines 221A, 221B may have anyappropriate shape so as to extend into the desired measurement site andto avoid contact with other contact plugs of circuit elements notbelonging to the support circuitry 220, while also the size andconfiguration of the interface portion 221I may be selected on the basisof layout or other considerations. It should be appreciated that othercontact elements may be formed prior to, commonly with or after theformation of the conductive lines 221A, 221B, depending on the overallprocess strategy. Furthermore, in some illustrative embodiments, anadditional dielectric material may be deposited so as to substantiallycompletely embed the conductive lines 221A, 221B in the interlayerdielectric material 205. Thereafter, well-established process techniquesto form actual contact elements may be applied.

FIG. 2 i schematically illustrates a portion of the element 221, inwhich the interface portion may have an essentially linearconfiguration, whereas, in other cases, any other appropriateconfiguration may be selected, in accordance with device requirements.

With reference to FIGS. 2 j-2 o, further illustrative embodiments willnow be described, in which a metal material may be used for at least oneof the conductive lines 221A, 221B, which may require appropriateconfinement so as to avoid undue interaction with the surroundingdielectric materials.

FIG. 2 j schematically illustrates a cross-sectional view correspondingto the line IIj in FIG. 2 i. As shown, the device 200 may comprise aplurality of circuit elements 213 which may belong to a circuit portionlocated within a measurement site of interest, such as the measurementsite 210 (FIG. 2 a). Moreover, in the manufacturing stage shown,trenches 224A, 224B may be formed in the dielectric layer 204, which, inthe embodiment shown, may additionally comprise a cap layer 206, whichmay provide enhanced metal confinement during the further processing.Moreover, an etch mask 207 is provided to define the trenches 224B, 224Aduring an etch process 208. Thus, the trenches 224A, 224B may be formedduring the common etch process 208, wherein, in a first etch step, itmay be etched through the cap layer 206 if provided, followed by an etchstep through the dielectric material 204 on the basis ofwell-established process techniques, wherein the layer 203 may act as anetch stop layer. Next, the etch mask 207 may be removed and,subsequently, a dielectric barrier layer may be formed on the dielectricmaterial 205 and within the openings 224A, 224B. For example, in someillustrative embodiments, a direct contact of a metal material, such ascopper, with a dielectric material of the layer 204 may be consideredinappropriate, since copper may readily diffuse in silicon dioxide basedmaterials. Thus, an appropriate dielectric barrier material, such assilicon nitride, silicon carbide and the like, may be provided as abarrier material, while not affecting the thermal and electricalcharacteristics of the conductive lines 221A, 221B still to be formed.

FIG. 2 k schematically illustrates the semiconductor device 200 in afurther advanced manufacturing stage, in which an appropriate etchprocess may have been performed to the remove the dielectric materialfrom the bottom of the trenches 224A, 224B, thereby exposing the contactplugs 222A, 222B that may have been previously formed as describedabove. In other illustrative embodiments, when the contact plugs 222A,222B are still to be formed, a further masking step may be performedprior to the etch process 207 by covering the trenches 224A, 224B whileexposing respective openings for the contact plugs and etching theexposed layer 203 in combination with the barrier material previouslydeposited. Thus, in this case, the contact regions 223C may be exposed(see FIGS. 2 d and 2 e) and the respective contact plugs may be formedin a common patterning sequence for the trenches 224A, 224B. In theembodiment shown in FIG. 2 k, it may be assumed that the contact plugsare already provided so that the dielectric barrier material may beremoved from horizontal device portions so as to expose the contactplugs 222A, 222B (FIG. 2 c). Hence, a respective sidewall spacer, actingas a barrier material with respect to the dielectric layer 204, may beprovided. It should be appreciated that the removal of the dielectricbarrier material from horizontal device portions may result in athickness reduction of the cap layer 206, while nevertheless reliablymaintaining a portion thereof so as to confine the dielectric materialof the layer 204.

FIG. 2 l schematically illustrates the semiconductor device 200 in afurther advanced manufacturing stage, in which an appropriate seed layer232 may be provided, which may be comprised of substantially the samematerial as is to be used for the conductive line 221B. For instance, ifthe line 221B is to be formed of copper, the seed layer 232 may also beprovided in the form of a copper material. For this purpose,well-established deposition techniques, such as sputter deposition andthe like, may be used.

FIG. 2 m schematically illustrates the device 200 in a further advancedstage in which the conductive line 221B is formed in the trench 224B,while a further resist mask 233 may cover the trench 224A and otherdevice regions outside the trench 224B. The conductive line 221B may beformed on the basis of well-established electrochemical depositiontechniques, in which, for instance, respective recipes for copper arewell established so as to obtain a desired bottom-to-top fill behavior,while the resist mask 233 efficiently restricts the copper growth to thetrench 224B. Thereafter, the mask 233 may be removed and the seed layer232 may also be removed, for instance, on the basis of anelectrochemical etch process and the like. It should be appreciated thata respective material loss of the conductive line 221B may be lesscritical, since a minor reduction of overall conductivity due to areduction of the cross-sectional area may not substantially negativelyaffect the thermoelectric effect. After the removal of the seed layer232, a further seed layer may be formed that has the appropriatematerial composition for the conductive line 221A. For instance, aconstantan material may be deposited, for instance, by sputterdeposition and the like. In still other illustrative embodiments, theseed layer 232 may be maintained and may be appropriately treated, forinstance, by incorporating nickel so as to obtain the desired alloy aswill also be used for the conductive line 221A. For this purpose, anappropriate plasma treatment, implantation techniques, a deposition ofnickel material with a subsequent thermal treatment and the like may beemployed.

FIG. 2 n schematically illustrates the device 200 after a furtherelectroplating process to fill the trench 224A with an appropriatematerial, such as a copper-nickel alloy, as previously explained. Duringthe corresponding electroplating process, the previously formed seedlayer 232 may act as a current distribution layer, wherein alsoappropriate deposition techniques may be used so as to ensure abottom-to-top fill behavior.

FIG. 2 o schematically illustrates the device 200 after the removal ofexcess material, for instance, by CMP and/or electrochemical polishingor etching and the like. Hence, a substantially planar surfacetopography may be provided, while the conductive lines, 221B, 221Areliably form the interface 221I between the different materials of thelines 221A, 221B. Since the respective seed layers 232, 234 arecomprised of the same material as the corresponding fill materials ofthe lines 221A, 221B, a “short circuit” of the interface 221I may beavoided. Furthermore, the seed layers 232, 234 may exhibit the sametemperature behavior with respect to the thermoelectric effect along thelines 221A, 221B, thereby ensuring the desired generation of thetemperature-dependent voltage at the contact plugs 222A, 222B withoutany interference of an unwanted third material component. Additionally,the sidewall spacers 231, with the etch stop layer 203, may providereliable confinement of the conductive materials in the lines 221A,221B, thereby eliminating the requirement for a conductive barriermaterial, which may otherwise significantly affect the overallthermoelectric behavior of the lines 221A, 221B.

It should be appreciated that the above-described process sequence mayalso be efficiently applied in situations in which the contact plugs222A, 222B are commonly filled with the conductive lines 221A, 221B.Hence, a “dual damascene” technique may be established for theconductive lines 221A, 221B and the contact plugs 222A, 222B.

With reference to FIGS. 2 p-2 r, further illustrative embodiments willnow be described in which the conductive lines may be embedded into adielectric material that allows direct contact with the material for theconductive lines.

FIG. 2 p schematically illustrates a cross-sectional view of the device200 wherein, in some illustrative embodiments, the layer 203 may beprovided with a substantially planar surface geometry, which may beaccomplished by providing the layer 203 with a sufficient thickness orby providing a plurality of individual layers, which may be subsequentlyplanarized. In some illustrative embodiments, a first dielectric layer,such as the layer 203 as previously illustrated, may be formed andpatterned so as to receive the contact plugs 222A, 222B. In otherillustrative embodiments, the contact plugs may be formed commonly withthe respective conductive lines as previously explained. Hence, afterproviding the dielectric material 203, its surface topography may beplanarized, for instance, by CMP. Next, in some illustrativeembodiments, an etch mask may be formed, such as the mask 207 as shownin FIG. 2 j, in order to define the trenches 224A, 224B in a commonpatterning process. In the embodiment shown, the trenches 224A, 224B maybe formed during individual patterning sequences, wherein an etch mask235 may define the position and lateral size of the trench 224B. Next,an etch process may be performed on the basis of the mask 235, which maybe stopped at any appropriate height, for instance, by connecting to thecontact plug 222B, if already provided. Thereafter, the mask 235 may beremoved and an appropriate seed layer may be deposited.

FIG. 2 q schematically illustrates the device 200 in a further advancedmanufacturing stage, in which the seed layer 232 has been used as anefficient current distribution layer for an electrochemical depositionprocess performed on the basis of appropriate process parameters so asto obtain the desired deposition fill behavior. For instance, the seedlayer and the electrochemically deposited material 236 may be comprisedof a copper material. Since the dielectric material 203 may suitablyconfine the material of the layers 232, 236, any further barriermaterial may not be required. Thereafter, any excess material may beremoved, for instance, by electrochemical etching, CMP and the like.Thereafter, a further etch mask may be formed in order to define therespective trench for the conductive line 221A, which may besubsequently filled with the deposition of an appropriate seed layerfollowed by an electrochemical deposition process.

FIG. 2 r schematically illustrates the device 200 after theabove-described process sequence. Hence, the seed layer 234 and theactual fill material layer 237 are provided, thereby defining theconductive line 221A adjacent and in contact with the conductive line221B. It should be appreciated that a reliable contact of the lines221A, 221B may be achieved by appropriately positioning the respectiveetch mask such that a portion of the line 221B may be exposed to theetch ambient and/or by applying a certain degree of isotropic componentduring the etch process, thereby reliably removing any dielectricmaterial at the interface 221I. Next, any excess material may beremoved, for instance, by CMP, and the further processing may becontinued, for instance, by depositing the dielectric material 204 andforming contact plugs for other circuit elements, such as the circuitelements 213.

Hence, a plurality of well-established process techniques and materials,such as copper, nickel and platinum, may be advantageously used whenforming the temperature-sensitive element 221 in the interlayerdielectric material 205, wherein a reliable confinement of certainmaterials may also be guaranteed, for instance, on the basis of theabove-described process techniques.

FIG. 3 schematically illustrates a top view of a semiconductor device300, which may comprise one or more temperature-sensitive elements 321,as previously described with reference to the device 200. Thus, the oneor more elements 321 may extend into respective measurement sites ofinterest 310, irrespective of any design constraints in the devicelayer, as previously explained. Furthermore, the device 300 may comprisea reference element 321R, which may extend into a region 310R of definedtemperature conditions during operation of the device, thereby providinga reliable temperature reference for the one or more elements 321connecting to the support circuitry 320. For example, the region 310Rmay be selected such that a desired temperature may be obtained, whichmay enable a reliable determination of a difference with respect tosignals obtained from other high temperature positions 310, thereby evenfurther enhancing the overall accuracy of the temperature management inthe device 300. Due to the principles disclosed herein, the referencearea 310R may be selected independently of a position of a supportcircuitry 320 and independently of any design constraints, which may beimposed on the device layer so that an appropriate reference point maybe selected for a plurality of temperature-sensitive elements 321. Forinstance, the location 310R may be selected so as to provide a stablereference point substantially without being affected by local hot spotsand the thermal gradient associated therewith.

Thus, based on a respective temperature-dependent voltage signalobtained by the one or more temperature-sensitive elements 221, 321, anefficient overall temperature monitoring and, thus, controlling of thedevice under consideration may be achieved. For instance, upon thedetection of an invalid temperature at a specified circuit portion, theoperating speed of the entire device or portions thereof may be reducedor respective circuit portions or the entire circuit may be shut down byan internally supplied control unit (not shown). In still otherillustrative embodiments, a corresponding temperature-dependent controlsignal may be supplied to an external device via I/O capabilities of thesemiconductor device under consideration or by a dedicated signal pathand the like.

FIG. 4 schematically illustrates a semiconductor device 400 in which aplurality of thermocouples 421 may be appropriately connected to eachother so as to enhance the overall control efficiency. For example, theplurality of thermocouples 421 may extend into a region of interest 410,which may represent a temperature-sensitive area, for instance, a hotspot and the like. As previously explained, the functional principle ofthermocouples resides in the fact that a temperature gradient mayestablish a voltage, which may be increased by connecting in series aplurality of the thermocouples 421, which, due to their common extensioninto the region 410, may be substantially connected in parallel withrespect to their thermal behavior. That is, since essentially the sametemperature conditions may prevail in the region 410, and thethermocouples 421 may terminate in a region having substantially thesame temperature, all of the thermocouples 421 may substantially respondin a very similar manner. Hence, a significantly increasedtemperature-dependent voltage may be generated. For example, for anillustrative thermocouple comprised of copper and constantan, atemperature difference of approximately 100° C. may result in a voltageof 4.3 mV. Thus, by a serial connection of a plurality of thethermocouples 421, well-detectable temperature-dependent voltages may becreated. Thus, the detection and response to even minute temperaturefluctuations may be increased on the basis of a correspondinglyincreased output voltage of the thermocouples 421.

In some illustrative embodiments, the voltage obtained by the pluralityof thermocouples 421 may be advantageously used to supply a significantportion thereof to the supply voltage of the device 400 which mayenhance the overall efficiency of the device 400 and may also contributeto an efficient heat dissipation from the region 410. As is well known,the creation of a thermoelectric voltage may result in a current flowwhen appropriately connecting the end portions of the thermocouples 421,thereby also resulting in a heat dissipation, since the induced currentflow may reduce the temperature at the hot side, while increasing thetemperature at the cold side of the thermocouples. Consequently, anadditional heat dissipation mechanism may be provided, whileconcurrently or alternatively a portion of the distributed heat may beconverted into electrical power which may be fed into the supply voltagesource of the device 400.

As a result, the present disclosure relates to methods and semiconductordevices in which temperature-sensitive elements may be provided withinthe contact structure of the device, thereby reducing the amount ofsemiconductor area occupied by temperature-related circuitry, whilenevertheless providing the potential of routing thetemperature-sensitive element to any desired device location. Thus,spatial coverage and accuracy of temperature control in semiconductordevices may be improved, while also enabling the employment ofwell-established process techniques and materials.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. For example, the process steps set forth above may beperformed in a different order. Furthermore, no limitations are intendedto the details of construction or design herein shown, other than asdescribed in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Accordingly, the protection sought herein is as set forth inthe claims below.

1. A semiconductor device, comprising: a semiconductor layer formedabove a substrate; a circuit element formed in said semiconductor layer,said circuit element comprising a contact region; an interlayerdielectric material formed above said circuit element; a contact elementformed in said interlayer dielectric material and connecting to saidcontact region; and a temperature-sensitive element formed in saidinterlayer dielectric material and configured to provide atemperature-dependent signal.
 2. The semiconductor device of claim 1,wherein said temperature-sensitive element comprises an interfaceportion and an extension portion connected thereto.
 3. The semiconductordevice of claim 2, wherein said interface portion comprises an interfaceformed by a first conductive material and a second conductive material,said first and second conductive materials differing in materialcomposition.
 4. The semiconductor device of claim 3, wherein saidextension portion comprises a first conductive line comprised of saidfirst conductive material and a second conductive line comprised of saidsecond conductive material.
 5. The semiconductor device of claim 2,wherein said interface portion is positioned in close proximity to saidcircuit element so as to enable determination of a local temperaturecaused by said circuit element during operation.
 6. The semiconductordevice of claim 1, wherein said interlayer dielectric material comprisesan etch stop layer and a dielectric layer formed above said etch stoplayer and wherein said temperature-sensitive element is at leastpartially formed in said dielectric layer.
 7. The semiconductor deviceof claim 6, further comprising one or more circuit elements formed insaid semiconductor layer and a first contact element and a secondcontact element formed in said interlayer dielectric material, saidfirst and second contact elements connecting said temperature-sensitiveelement to said one or more circuit elements.
 8. The semiconductordevice of claim 7, wherein said temperature-sensitive element comprisesa first conductive line connected to said first contact element and asecond conductive line connected to said second contact element.
 9. Thesemiconductor device of claim 1, further comprising a secondtemperature-sensitive element formed in said interlayer dielectricmaterial, said second temperature-sensitive element positioned in alocation corresponding to a lower gradient of operating temperaturescompared to a gradient of operating temperatures corresponding to alocation of said temperature-sensitive element.
 10. A semiconductordevice, comprising: a plurality of circuit elements formed in and abovea semiconductor layer; an interlayer dielectric material enclosing saidplurality of circuit elements; and a thermocouple formed in saidinterlayer dielectric material.
 11. The semiconductor device of claim10, wherein said thermocouple comprises a first conductive line and asecond conductive line, said first and second conductive lines definingan interface.
 12. The semiconductor device of claim 11, furthercomprising a first contact element and a second contact element, saidfirst and second contact elements connecting said first and secondconductive lines to one or more of said circuit elements.
 13. Thesemiconductor device of claim 10, further comprising a referencethermocouple, wherein said reference thermocouple is positioned at alocation having a lower temperature during operation compared to atemperature corresponding to a location of said thermocouple.
 14. Thesemiconductor device of claim 11, wherein said thermocouple comprises afirst metal in said first conductive line and a second metal in saidsecond conductive line, said first and second metals differing from eachother.
 15. The semiconductor device of claim 12, wherein said interlayerdielectric material comprises an etch stop layer and a dielectric layerand wherein said first and second contact elements are formed in saidetch stop layer and said first and second conductive lines are formed insaid dielectric layer.
 16. The semiconductor device of claim 11, whereinsaid thermocouple comprises copper.
 17. A method, comprising: selectinga first location in an overall circuit design of a semiconductor device,said first location corresponding to a device area for receiving atemperature signal by a temperature evaluation circuit of saidsemiconductor device; selecting a second location as a measurement siteof interest in said semiconductor device; and forming atemperature-sensitive element in an interlayer dielectric materialformed between circuit elements of said semiconductor device and a firstmetallization layer of said semiconductor device, saidtemperature-sensitive element comprising conductive lines extending fromsaid first location to said second location.
 18. The method of claim 17,further comprising forming said conductive lines in a first dielectriclayer formed above a second dielectric layer, wherein said first andsecond dielectric layers at least partially form said interlayerdielectric material.
 19. The method of claim 18, further comprisingforming contact elements in said second dielectric layer, said contactelements connecting said conductive lines with at least some of saidcircuit elements.
 20. The method of claim 17, wherein forming saidconductive lines comprises forming a first conductive line comprising afirst conductive material and forming a second conductive linecomprising a second conductive material differing from said firstconductive material.
 21. The method of claim 20, further comprisingforming an interface between said first conductive line and said secondconductive line, wherein said interface is positioned at said secondlocation.
 22. The method of claim 20, wherein forming said conductivelines comprises depositing at least one of said first and secondconductive materials at least partially by performing an electrochemicaldeposition process.
 23. The method of claim 17, further comprisingselecting a third location acting as a temperature reference positionand forming a reference temperature-sensitive element for detecting atemperature at said third location.
 24. The method of claim 23, whereinsaid third location corresponds to a device area having a lowertemperature during operation compared to said second location.
 25. Themethod of claim 17, further comprising providing a plurality oftemperature-sensitive elements within a specified device area andcontrolling a temperature of said specified device area on the basis ofan electrical output power supplied by said plurality oftemperature-sensitive elements.